Hardware Solution of a First-Order Diophantine Equation

In this paper we present the theoretical framework for enumerating the solutions of the Diophantine equation (1) that helps us define the sets of points, of a nested loop, that can be executed in parallel. The analytical expression for finding those points is given below: + + + = 1 2 ... n i i i c (1) where i1, i2,..., in, ≤ ≤ ∀ = 0 , 1 ... p p i L p n are the loop indices, Lp is the loop bound and c defines the time all points satisfying this equation will be executed in parallel. Moreover, we present an innovative “refined” algorithm which speeds up the generation of those solutions compared to the traditional ‘brute-force” approach. Finally, we present a modular hardware implementation of this “refined” algorithm on FPGA platforms, an approach which increases even more the algorithm’s performance. The presented architecture and theoretical solution is suitable in load balancing applications, consisting of nested for-loops with dependencies, since it allows rapid and dynamic generation (in hardware) of the index points of loop instances that can be executed in parallel and can be easily reconfigured. Both the theoretical framework and the algorithmic solution are used for the enumeration and generation of the index values of loop instances to be executed in parallel (the “Point Generator” module in Fig.1) in a load balancing application which is a part of a more general project that proposes a Flexible General-Purpose Parallelizing Architecture for Nested Loops in Reconfigurable Platforms. The general architecture of the proposed design is illustrated in Fig.1 . Figure 1 The system’s architecture The critical module of the architecture presented in Fig.1 is the “Point Generator” component which generates the solutions of Equation (1). To preserve the generality through modularity 1 This work is co funded by the European Social Fund (75%) and National Resources (25%) Operational Program for Educational and Vocational Training II (EPEAEK II) and particularly the Program PYTHAGORAS II. of the approach, the “Point Generator” is implemented in hardware as a line of smaller interconnected modules defined as I-modules as shown in Fig.2. This implementation falls into the category of dynamic generation of index points of loop instances that can be executed in parallel as opposed to the static generation of those points. Static generation entails the computation of such points at design time and its storage in a memory and as a consequence consumes a greater amount of resources. To the extent of the authors’ knowledge, the implementation presented for the dynamic generation of those points (i.e. dynamic scheduling algorithms of nested loops with dependences) in hardware is innovative. Equation (1) is a first-order Diophantine equation with unitary coefficients. The problem for finding and enumerating its solutions is formulated as follows: Find all vectors 1 2 ( , ,..., ), ,0 , 1.. n p p p i i i i N i L p n ∈ ≤ ≤ ∀ = that are solutions to the equation + + + = 1 2 ... n i i i c We define the function fc(D) as the function that returns the desired result for a given c, D (where c is defined above and D is the depth of the nested loops, equals to n) and we prove that it is: 1 1